1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of fabricating the same. More particularly, the present invention relates to a semiconductor memory device having a multiple tunnel junction pattern and a method of fabricating the same.
2. Description of the Related Art
Advantages of dynamic random access memory (DRAM) include higher integration in a limited area than a memory device, such as static random access memory (SRAM), and faster operation speed than a memory device, such as a flash memory. A disadvantage of DRAM, however, is that it must be refreshed periodically in order to retain stored data. Thus, the DRAM consumes power even in a stand-by mode.
On the contrary, a non-volatile memory device such as a flash memory device has the advantage that periodic refreshes are unnecessary. The non-volatile memory device, however, has several disadvantages such as a high voltage demand for programming or erasing memory cells and slow operation speed in comparison with a DRAM or an SRAM. Thus, a new memory device uniting DRAM with flash memory has been developed.
FIG. 1 illustrates a diagram showing a unit cell of a semiconductor memory device having a conventional multiple tunnel junction pattern.
Referring to FIG. 1, a unit cell of a semiconductor memory device includes a planar transistor and a vertical transistor. The planar transistor is formed at a predetermined region of a semiconductor substrate 100, and includes a drain region 124d, a source region 124s and a floating gate 104. The drain region 124d and the source region 124s are spaced apart from each other. The floating gate 104 is arranged on a channel region between the drain region 124d and the source region 124s. The drain region 124d corresponds to a bit line and the floating gate 104 corresponds to a storage node. A gate insulating layer 102 is interposed between the storage node 104 and the channel region.
A multiple tunnel junction pattern 110 and a data line 122 are sequentially stacked on the storage node 104. The multiple tunnel junction pattern 110 includes semiconductor layers 106 and tunnel insulating layers 108, which are alternately and repeatedly stacked. An utmost top layer of the multiple tunnel junction pattern 110 may be either the semiconductor layer 106 or the tunnel insulating layer 108. The data line 122 is extended to be electrically connected with a plurality of adjacent memory cells. A gate interlayer dielectric layer 126 covers sidewalls of the multiple tunnel junction pattern 110 and the data line 122. The gate interlayer dielectric layer 126 also covers the data line 122.
A word line 128 is arranged on the gate interlayer dielectric layer 126 to cross over the data line 122. The word line 128 overlaps with the storage node 104 and the multiple tunnel junction pattern 110. The data line 122, the multiple tunnel junction pattern 110, the storage node 104 and the word line 128 form the vertical transistor. The data line 122 corresponds to a drain of the vertical transistor, and the storage node 104 corresponds to a source of the vertical transistor.
FIG. 2A illustrates an energy band diagram of a conventional semiconductor memory device, taken along line I–I′ of FIG. 1.
FIG. 2B illustrates an energy band diagram of a conventional semiconductor memory device, taken along line II–II′ of FIG. 1.
Referring to FIGS. 2A and 2B, the multiple tunnel junction pattern 110 of FIG. 1 has a plurality of high potential barriers provided by the tunnel insulating pattern 108. Generally, the semiconductor layer 106 is formed of an undoped silicon layer, and the word line 128 and the storage node 104 are formed of a P-type silicon layer and an N-type silicon layer, respectively. As illustrated in FIG. 2A, an accumulation layer is formed on sidewalls of the semiconductor layer 106 by an influence of the P-type word line 128. Therefore, the tunnel insulating pattern 108 adjacent to the gate dielectric layer 126 to a predetermined distance forms a relatively high potential barrier. As a result, in the stand-by mode, charges may leak out through a central region of the tunnel insulating pattern 108 having a relatively low potential barrier.